1-wire port expander

Memory pages

Address space of the device consists of 4 memory pages, each 8 bytes in size:

Page	Addresses	Contents
0	0x00 .. 0x07	ADC results
1	0x08 .. 0x0f	Control/status data
2	0x10 .. 0x17	Thresholds
3	0x18 .. 0x1f	User data, control/status data

The entire address space is available for reading and writing. Reading and writing data from/to memory addresses is byte-by-byte (commands 0xAA READ MEM, 0x55 WRITE MEM). ADC results are 16-bit values that are written into two memory cells by the device itself asynchronously after ADC conversion is completed sequentially for each channel (the conversion is initiated by 0x3c CONVERT command), the low and high bytes of ADC result are read from device atomically (the situation of reading low byte of old result and high byte of new result is excluded). When writing bytes that change port settings, the changes occur immediately after each byte is written.

Alarm flags

Device has 14 alarm flags: POR, AFD[0..4], AFL[0.2..4], AFH[0.2..4], if at least one of which is set, the device will respond to alarm search request. The device itself can change state of the flags (see description of the corresponding flags). All flags are also available for reading and changing by referring to bits at specific addresses. To exclude a device from alarm list, all of the alarm flags must be cleared.

Addresses 0x00..0x07

Bit	7	6	5	4	3	2	1	0
Address 0x00	ADCV0:[7..0]
Address 0x01	ADCV0:[15..8]
Address 0x02	ADCV2:[7..0]
Address 0x03	ADCV2:[15..8]
Address 0x04	ADCV3:[7..0]
Address 0x05	ADCV3:[15..8]
Address 0x06	ADCV4:[7..0]
Address 0x07	ADCV4:[15..8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

ADCV[0,2..4] - value of the last ADC result on port P[0,2..4], 2 bytes, the LSB first. Always 16-bit value: regardless of the resolution (RES), the result is always left-shifted so that the most significant bit is in the 15th position, the least significant bits are cleared.

Addresses 0x08, 0x0a, 0x0c, 0x0e

Bit	7	6	5	4	3	2	1	0
Address 0x08	OE0	OC0	DI0	REF0	RES0:[3..0]
Address 0x0a	OE2	OC2	DI2	REF2	RES2:[3..0]
Address 0x0c	OE3	OC3	DI3	REF3	RES3:[3..0]
Address 0x0e	OE4	OC4	DI4	REF4	RES4:[3..0]
Access	R/W	R/W	R	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

OE[0,2..4] and OC[0,2..4] - port P[0,2..4] operation mode:

OE	OC	Port mode
0	0	High impedance state
0	1	A pull-up resistor is connected between input and VCC
1	0	Output logical 0 (low)
1	1	Output logical 1 (high)

Setting output port mode does not disable input capability (reading/monitoring logical level or ADC function) of port.

DI[0..4] (bit DI1 for port P1 is located in byte at address 0x1f) - current logical level read from port P[0..4], 0 - low, 1 - high.

REF[0,2..4] - ADC reference voltage for port P[0,2..4], will be used for subsequent ADC. Indicates the conversion range for the ADC, any exceeding voltage will result in maximum ADC value.

REF	Reference voltage
0	VCC
1	Internal 1.1V

RES[0,2..4] - ADC resolution in bits (from 1 to 15, value 0 corresponds to 16 bits) for port P[0,2..4], will be used for subsequent ADC.

Addresses 0x09, 0x0b, 0x0d, 0x0f

Bit	7	6	5	4	3	2	1	0
Address 0x09	POR	AFD0	AFH0	AFL0	AEH0	AEL0	AED0	AWD0
Address 0x0b	POR	AFD2	AFH2	AFL2	AEH2	AEL2	AED2	AWD2
Address 0x0d	POR	AFD3	AFH3	AFL3	AEH3	AEL3	AED3	AWD3
Address 0x0f	POR	AFD4	AFH4	AFL4	AEH4	AEL4	AED4	AWD4
Access	R/W	R/C	R/W	R/W	R/W	R/W	R/W	R/W
Default	1	0	0	0	1	1	0	0

POR - power-on reset flag, 0 - cleared, 1 - set. The device itself can only set this flag, which means that all settings have been reset to default. User can write 0 or 1 (but writing 1 will not generate a reset cycle). Flag is updated simultaneously in all four bytes.

AFD[0..4] (bit AFD1 for port P1 is located in byte at address 0x1f, but in a bit with a different number!) - logical level alarm flag of port P[0..4], 0 - cleared, 1 - set. By the user this flag can only be cleared by writing 1, writing 0 keeps flag unchanged:

Writing to AFD	AFD
0	unchanged
1	0

By the device itself this flag can only be set and only if corresponding alarm enable bit AED[0..4] is set to 1 and the logical level of port P[0..4] (0 - low, 1 - high) matches the corresponding value of the AWD[0..4] bit, otherwise flag remains unchanged:

AED	AWD	Port logical level	AFD
0	any	any	unchanged
1	0	always high	unchanged
1	0	detected low	1
1	1	always low	unchanged
1	1	detected high	1

AFL[0,2..4] / AFH[0,2..4] - analog value too low/high (below THL[0.2..4] / above THH[0.2..4] threshold) alarm flag, 0 - cleared, 1 - set. User can write 0 or 1. By the device itself this flag is set only if the corresponding alarm enable bit AEL[0.2..4] / AEH[0.2..4] is set to 1 and analog value is outside the corresponding threshold, otherwise flag is cleared. Both flags are updated after the ADC is completed and written for the corresponding port, the flags of the port for which ADC was not performed remain unchanged:

ADC was performed on port	AEL	ADC result	AFL
no	any		unchanged
yes	0	does not matter	0
yes	1	ADCV:[15..8] >= THL	0
yes	1	ADCV:[15..8] < THL	1

ADC was performed on port	AEH	ADC result	AFH
no	any		unchanged
yes	0	does not matter	0
yes	1	ADCV:[15..8] <= THH	0
yes	1	ADCV:[15..8] > THH	1

When compared to the threshold, only the high byte of the ADC result is used.

AEL[0,2..4] / AEH[0,2..4] - enable analog low/high alarm for port P[0,2..4] (see tables of states in AFL[0.2..4] / AFH[0.2..4] bits description).

AED[0..4] (bit AED1 for port P1 is located in byte at address 0x1f) - enable logical level alarm for port P[0..4] (see table of states in AFD[0..4] bit description).

AWD[0..4] (bit AWD1 for port P1 is located in byte at address 0x1f) - monitored logical level of port P[0..4] (0 - low, 1 - high), upon detection of which the alarm flag is set (see table of states in AFD[0..4] bit description).

Addresses 0x10, 0x12, 0x14, 0x16

Bit	7	6	5	4	3	2	1	0
Address 0x10	THL0:[7..0]
Address 0x12	THL2:[7..0]
Address 0x14	THL3:[7..0]
Address 0x16	THL4:[7..0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

THL[0,2..4] - low threshold value for the analog signal on port P[0,2..4], if ADC result is lower than this value, alarm flag is set (see table of states in AFL[0,2..4] / AFH[0,2..4] bits description).

Addresses 0x11, 0x13, 0x15, 0x17

Bit	7	6	5	4	3	2	1	0
Address 0x11	THH0:[7..0]
Address 0x13	THH2:[7..0]
Address 0x15	THH3:[7..0]
Address 0x17	THH4:[7..0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	1	1	1	1	1	1	1	1

THH[0,2..4] - high threshold value for the analog signal on port P[0,2..4], if ADC result is higher than this value, alarm flag is set (see table of states in AFL[0,2..4] / AFH[0,2..4] bits description).

Address 0x1e

Bit	7	6	5	4	3	2	1	0
Address 0x1e	PWM1:[7..0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	1	1	1	1	1	1	1	1

PWM1 - sets the duty cycle of signal on port P1 in PWM mode (OE1 = 1, OC1 = 1), in other modes the parameter does not affect anything. The result duty cycle will be: S = (PWM1 + 1) / 256. The duty cycle S = 0 can be obtained by setting port mode OE1 = 1, OC1 = 0. Setting PWM1 = 255, OE1 = 1, OC1 = 1 corresponds to output logical 1 (high) on port P1.

Address 0x1f

Bit	7	6	5	4	3	2	1	0
Address 0x1f	OE1	OC1	DI1	unused	unused	AFD1	AED1	AWD1
Access	R/W	R/W	R	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

OE1 and OC1 - port P1 operation mode:

OE	OC	Port mode
0	0	High impedacne state
0	1	A pull-up resistor is connected between input and VCC
1	0	Output logical 0 (low)
1	1	Output PWM signal

Setting output port mode does not disable input capability (reading/monitoring logical level) of port.

DI1, AFD1, AED1, AWD1 - see DI[0..4], AFD[0..4], AED[0..4], AWD[0..4] bits description respectively.

User data

Bit	7	6	5	4	3	2	1	0
Address 0x18	unused
Address 0x19	unused
Address 0x1a	unused
Address 0x1b	unused
Address 0x1c	unused
Address 0x1d	unused
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Addresses are not used by the device, they can be used to store user data.